In a highly integrated system, a large number of modules are idle at any given time. The ever increasing reduction in threshold voltage, channel length and gate oxide thickness has resulted in a significant increase in the leakage current of idle devices. This increase in leakage current significantly undermines the reduction in power consumption. As a result, both the static and dynamic power consumption of the system remains significantly high. This factor is assuming increasing importance in large System-On-Chip (SoC) devices. In deep submicron technologies involving several million gates, static power dissipation itself becomes comparable to or more than the dynamic power. Every attempt is therefore made to reduce the static leakage component for sleep as well as dynamic modes, especially for low power applications.
A major contributor of leakage current in a very large variety of digital systems are the buffer chains used to buffer the signals going out of the device to the pads. These buffer chains comprise large transistors due to the relatively higher current levels that are required to be handled by them. Due to their larger size, the leakage currents in these chains are relatively large. Buffer chains are ordinarily turned off when in a tri-state mode or when the pad is selected for an input mode. Currently, buffer chains are generally powered on with the help of power gating circuits.
Power gating is a well known feature specifically used to reduce leakage power in semiconductor devices. In the power gating technique a sleep transistor is introduced between the power supply source and circuits fed by the power source. These sleep transistors are turned off in the sleep mode to provide isolation from the power supply and cut off the supply leakage path. FIG. 1 shows isolation of a logic module from a power supply with the help of a gating transistor as known in the prior art. Control (11) is applied to the gating transistor (12) that delivers power to the logic block (13).
A similar arrangement uses a diode connected in parallel with the device to maintain the logic value between a reduced logic high and the low value. The ground connection can also be gated with such an arrangement. However, implementation of this arrangement results in a large area overhead and is difficult to apply for all the components of the design. Complete power gating without the use of diodes results in data loss, and requires the reinitialization of the system resulting in a large reactivation time.